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[Embeded-SCM Develop] cpld_fpga_source_code

Description: cpld fpga 一些应用实例程序的源代码. -cpld fpga application procedures for some of the source code.
Platform: | Size: 289792 | Author: 大为 | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] Pc104_Cpld

Description: 是关于对数据采集卡的基于PC104总线的读写程序，开发环境Quarters , 用VHDL语言编写。-is on the right data acquisition card based on the PC104 literacy procedures, Quarters development environment using VHDL language.
Platform: | Size: 319488 | Author: 陈伟 | Hits:

[Embeded-SCM Develop] st_11

Description: cpld状态及设计。 很好的文章。 要设计vhdl状态机的话，最好看看。-cpld state and design. Good paper. Vhdl to design the state machine, the best look.
Platform: | Size: 113664 | Author: wang | Hits:

[Embeded-SCM Develop] vhdlcodes2

Description: FPGA/CPLD集成开发环境ISE使用详解实例－2-FPGA/CPLD integrated development environment IDE ISE examples-2
Platform: | Size: 17408 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcodes3

Description: FPGA/CPLD集成开发环境ISE使用详解实例－3-FPGA/CPLD integrated development environment IDE ISE example-3
Platform: | Size: 74752 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcodes4

Description: FPGA/CPLD集成开发环境ISE使用详解实例－4-FPGA/CPLD integrated development environment IDE ISE example-4
Platform: | Size: 149504 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcdes6

Description: FPGA/CPLD集成开发环境ISE使用详解实例－6-FPGA/CPLD integrated development environment IDE ISE example-6
Platform: | Size: 19456 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90112 | Author: 王雪松 | Hits:

[VHDL-FPGA-Verilog] vhdl_clock

Description: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 324608 | Author: 赵海东 | Hits:

[VHDL-FPGA-Verilog] vhdl_i2c

Description: 7． IIC 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址，按动另 外一个键，将刚写入的数据读回CPLD，并在数码管上显示。帮助读者掌握I2C 的总线协 议和EEPROM 的读写方法。-7. IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data switch E EPROM a certain address, pressed another button, just write the data back to reading CPLD, and the digital pipe show. To help readers master the I2C bus protocol and EEPROM read and write methods.
Platform: | Size: 419840 | Author: 赵海东 | Hits:

[VHDL-FPGA-Verilog] taxi_counter

Description: 用VHDL编写的一个出租车计费器，起步6元计2公里，此后每半公里计0.8元，停车等待每2.5分计0.8元。通过仿真，但未下载到CPLD测试-a taxi prepared by the accounting device, starting six yuan or 2 km, then every half kilometer or 0.8 yuan, stopping to wait for every 2.5 minutes or 0.8 yuan. Through simulation, but not download to test CPLD
Platform: | Size: 242688 | Author: 尚方喆 | Hits:

[Software Engineering] ddsbyvhdl

Description: 摘要：介绍了基于可编程逻辑器件CPLD和直接数字频率合成技术（DDS）的三相多波形函数发生器的基本原理，并在此基础上给出了基于CPLD的各模块设计方法及其VHDL源程序-Abstract : Based on the CPLD and direct digital frequency synthesis (DDS) of a three-phase multi-function waveform Generator to the basic principles and on this basis given the CPLD based on the module design and VHDL source
Platform: | Size: 47104 | Author: 陈鑫 | Hits:

[Embeded-SCM Develop] vhdlcodes7

Description: FPGA/CPLD集成开发环境ise的使用详解 示例代码7-FPGA/CPLD integrated development environment IDE ise the sample code 7
Platform: | Size: 95232 | Author: bigbibby | Hits:

[Embeded-SCM Develop] vhdlcodes9

Description: FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA/CPLD Integrated Development Environment ise Comments on the use of code examples 9
Platform: | Size: 5120 | Author: bigbibby | Hits:

[Embeded-SCM Develop] vhdlcodes10

Description: FPGA/CPLD集成开发环境ise的使用详解 示例代码10-FPGA/CPLD integrated development environment IDE ise the example code 10
Platform: | Size: 8192 | Author: bigbibby | Hits:

[Embeded-SCM Develop] vhdlcodes11

Description: FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA/CPLD integrated development environment IDE ise the example code
Platform: | Size: 4096 | Author: bigbibby | Hits:

[Other Embeded program] altera_USB_blaste

Description: altera USB blaste 制作全套资料。包括原理图、93LC46的配置文件和CPLD的VHDL源程序。-altera USB blaste produced full set of information. Including drawings, 93LC46 configuration files and CPLD VHDL source.
Platform: | Size: 137216 | Author: xuphone | Hits:

[Books] changyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793600 | Author: 1 | Hits:

[Books] rommatlab

Description: 错误检测与纠正电路的设计与实现用VHDL语言在CPLD上实现串行通信.doc-error detection and correction circuit design and implementation using VHDL on the CPLD serial communications. D oc
Platform: | Size: 212992 | Author: 1 | Hits:
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